`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module yue_dffl # (
  parameter DW = 32
) (
    input                  ld, 
    input         [DW-1:0] din,
    output   reg  [DW-1:0] q = 0,

    input                  clk
);



always @(posedge clk )
   if (ld)
    q <= #1 din;




`ifdef SIM//{
//synopsys translate_off
fii_xchecker # (
  .DW(1)
) fii_xchecker(
  .i    (ld),
  .clk  (clk)
);
//synopsys translate_on
`endif//}

    

endmodule
